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Tripath Technology, Inc. - Technical Information
TA2021B STEREO 25W (4) CLASS-TTM DIGITAL AUDIO AMPLIFIER DRIVER USING DIGITAL POWER PROCESSING (DPPTM) TECHNOLOGY
Technical Information Revision 4.0 - July 2003
General Description
The TA2021B is a 25W (4) continuous average per channel Class-T Digital Audio Power Amplifier IC using Tripath's proprietary Digital Power Processing (DPPTM) technology. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
Applications
DVD Receivers Mini/Micro Component Systems Computer / PC Multimedia Cable Set-Top Products Televisions Battery Powered Systems
Features
Class-T architecture Single Supply Operation "Audiophile" Quality Sound 0.05% THD+N @ 13W 4 0.1% THD+N @15.5W 4 0.1% IHF-IM @ 1W 4 High Power 25W @ 4, 10% THD+N, VDD=14.6V 23.5W @ 4, 10% THD+N, VDD=14.2V 14W @ 8, 10% THD+N, VDD=14.2V High Efficiency 88% @ 13.5W 8 81% @ 25W 4 Dynamic Range = 100 dB Mute and Sleep inputs Turn-on & turn-off pop suppression Over-current protection Over-temperature protection Bridged outputs 36-pin PSOP "Slug-Up" package
Benefits
Fully integrated solution with internal FETs Easier to design-in than Class-D Dramatically improves efficiency versus Class-AB amplifiers Signal fidelity equal to high quality linear amplifiers High dynamic range compatible with digital media such as CD and DVD, and internet audio
Typical Performance
THD+N vs Output Power
10 5 2 THD+N (%) 1 0.5 0.2 0.1
RL=4 RL=8
VDD=14.2V Av=12V/V BW=22-22kHz
0.05 0.02 0.01
600m
1
2
3
4
5 6 789
20
Output Power (W)
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Absolute maximum ratings (Note 1)
SYMBOL VDD V5 SLEEP MUTE TSTORE TA TJ Supply Voltage Input Section Supply Voltage SLEEP Input Voltage MUTE Input Voltage Storage Temperature Range Operating Free-air Temperature Range Junction Temperature PARAMETER Value 16 6.0 -0.3 to 6.0 -0.3 to V5+0.3 -40 to 150 -40 to 85 150 UNITS V V V V C C C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. See the table below for Operating Conditions. Note 2: Human body model, 100pF discharged through a 1.5K resistor. Note 3: Machine model, 220pF discharged through all pins.
Operating Conditions (Note 4)
SYMBOL VDD VIH VIL Supply Voltage High-level Input Voltage (MUTE, SLEEP) Low-level Input Voltage (MUTE, SLEEP) PARAMETER MIN. 8.5 3.5 1 TYP. 14.2 MAX. 14.6 UNITS V V V
Note 4: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits.
Thermal Characteristics
SYMBOL JC JA PARAMETER Junction-to-case Thermal Resistance Junction-to-ambient Thermal Resistance (still air) VALUE UNITS 2.5 50 C/W C/W
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Electrical Characteristics (Notes 6, 7)
See Test/Application Circuit. Unless otherwise specified, VDD = 14.2V, f = 1kHz, Measurement Bandwidth = 22kHz, RL = 4, TA = 25 C.
SYMBOL PO PARAMETER Output Power (Continuous Average/Channel) CONDITIONS THD+N = 0.1% THD+N = 10% PO Output Power (VDD=14.6V) (Continuous Average/Channel) THD+N = 0.1% THD+N = 10% IDD,MUTE IDD, SLEEP Iq THD + N IHF-IM SNR CS PSRR VOFFSET VOH VOL eOUT Mute Supply Current Sleep Supply Current Quiescent Current Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Power Supply Rejection Ratio Power Efficiency Output Offset Voltage High-level output voltage (FAULT & OVERLOADB) Low-level output voltage (FAULT & OVERLOADB) Output Noise Voltage MUTE = VIH SLEEP = VIH VIN = 0 V PO = 10W/Channel 19kHz, 20kHz, 1:1 (IHF) A-Weighted, POUT = 25W, RL = 4 0dBr = 1W, RL = 4, f = 1 kHz Vripple = 100mV POUT = 13.5W/Channel, RL = 8 No Load, MUTE = Logic low 3.5 1 A-Weighted, input AC grounded 100 74 60 RL = 4 RL = 8 RL = 4 RL = 8 RL = 4 RL = 8 RL = 4 RL = 8 MIN. TYP. 15.5 9 23.5 14 16.5 9.5 25 14.8 5.5 0.25 64 0.035 0.1 100 80 80 88 50 150 0.3 7 2 75 MAX. UNITS W W W W W W W W mA mA mA % % dB dB dB % mV V V V
Note 6: Note 7:
Minimum and maximum limits are guaranteed but may not be 100% tested. For operation in ambient temperatures greater than 25C, the device must be de-rated based on the maximum junction temperature and the thermal resistance determined by the mounting technique.
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Pin Description
Pin 2, 3 Function DCAP2, DCAP1 Description Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted 10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal), frequency, and phase as DCAP1. Digital 5VDC, Analog 5VDC Analog Ground
4, 9 5, 8, 17 6 7 10, 14 11, 15 12 16 18 19 20, 35 22 24, 27; 31, 28 25, 26, 29, 30 13, 21, 23, 32, 34 33 36 1
V5D, V5A AGND1, AGND2, AGND3 REF OVERLOADB OAOUT1, OAOUT2 INV1, INV2 MUTE BIASCAP SLEEP FAULT PGND2, PGND1 DGND OUTP2 & OUTM2; OUTP1 & OUTM1 VDD2, VDD2 VDD1, VDD1 NC VDDA CPUMP 5VGEN
Internal reference voltage; approximately 1.0 VDC. A logic low output indicates the input signal has overloaded the amplifier. Input stage output pins. Single-ended inputs. Inputs are a "virtual" ground of an inverting op-amp with approximately 2.4VDC bias. When set to logic high, both amplifiers are muted and in idle mode. When low (grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. This pin should be tied to GND if not used. Input stage bias voltage (approximately 2.4VDC). When set to logic high, device goes into low power mode. If not used, this pin should be grounded A logic high output indicates thermal overload, or an output is shorted to ground, or another output. Power Grounds (high current) Digital Ground Bridged outputs Supply pins for high current H-bridges. Not connected. Not bonded internally. Supply pin for analog section. Charge pump output (nominally 10V above VDDA) Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
TA2021B Pinout
36-pin Slug-Up SOP Package (Top View)
CPUMP PGND1 NC VDDA NC OUTP1 VDD1 VDD1 OUTM1 OUTM2 VDD2 VDD2 OUTP2 NC DGND NC PGND2 FAULT 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 +5VGEN DCAP2 DCAP1 V5D AGND1 REF OVERLOADB AGND2 V5A OAOUT1 INV1 MUTE NC OAOUT2 INV2 BIASCAP AGND3 SLEEP
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Application / Test Circuit
TA2021B
CI 2.2uF +
OAOUT1 10 RF 20K INV1 11
VDD1
31
VDD1 (pin 29,30) Lo DH 10uH, 2A
OUTP1 DO (Pin 35)
RI 20K CA 0.1uF (Pin 8) 5V
BIASCAP
16
5V
Processing & Modulation
PGND1 VDD1
(Pin 35) VDD1 (pin 29,30) Lo DH 10uH, 2A
OUTM1 DO
*Co 0.47uF
CZ 0.47uF CDO 0.1uF RZ 10, 1/2W RL 4 or *8
28
*Co 0.47uF
MUTE
12
PGND1
(Pin 35)
FAULT OVERLOADB
19
OAOUT2 14
7
VDD2
CI 2.2uF +
RF 20K RI 20K
INV2 15
24
VDD2 (pin 25,26) Lo DH 10uH, 2A OUTP2 DO
6
RREF (Pin 8) 8.25K, 1%
REF
Processing & Modulation
PGND2 VDD2
(Pin 20) (Pin 20) VDD2 (pin 25,26) Lo DH 10uH, 2A OUTM2 DO
*Co 0.47uF
CZ 0.47uF CDO 0.1uF
3
+12V 1M 0.1uF CD 0.1uF
DCAP1
27
RZ *Co 0.47uF 10, 1/2W
RL 4 or *8
2 18 4
DCAP2
PGND2
SLEEP CPUMP 36
(Pin 20)
+
V5D AGND1 V5A AGND2 AGND3
5V
CS 0.1uF To Pin 1
VDDA DGND +5VGEN VDD1 VDD1
33 22 1 30 29
CP 1uF CS 0.1uF CS 0.1uF To Pins 4,9
5 9
CS 0.1uF
8 17
PGND1 35
CSW 0.1uF
+
VDD (14.2V) CSW
180uF, 16V
13 21 23 32 34
25 VDD2
NC VDD2 PGND2
26 20
CSW 0.1uF
+
CSW 180uF, 16V
Note: Analog and Digital/Power Grounds must be connected locally at the TA2021 Analog Ground Digital/Power Ground All Diodes Motorola MBRS130T3 * Use C o = 0.22F and Cz = 0.22F for 8 Ohm loads
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External Components Description
Components Description
(Refer to the Application/Test Circuit)
RI RF
CI RREF CA CD CP
Inverting Input Resistance to provide AC gain in conjunction with RF. This input is biased at the BIASCAP voltage (approximately 2.4VDC). Feedback resistor to set AC gain in conjunction with RI; A V = 12(RF / RI ) . Please refer to the Amplifier Gain paragraph in the Application Information section. AC input coupling capacitor which, in conjunction with RI, forms a highpass filter at fC = 1 (2RICI ) Bias resistor. Locate close to pin 6 and ground at pin 8. BIASCAP decoupling capacitor. Should be located close to pin 16. Charge pump input capacitor. This capacitor should be connected directly between pins 2 and 3 and located physically close to the TA2028. Charge pump output capacitor that enables efficient high side gate drive for the internal H-bridges. To maximize performance, this capacitor should be connected directly between pin 36 (CPUMP) and pin 34 (VDDA). Please observe the polarity shown in the Application/ Test Circuit. Supply decoupling for the low current power supply pins. For optimum performance, these components should be located close to the pin and returned to their respective ground as shown in the Application/Test Circuit. Supply decoupling for the high current, high frequency H-Bridge supply pins. These components must be located as close to the device as possible to minimize supply overshoot and maximize device reliability. Both the high frequency bypassing (0.1uF) and bulk capacitor (180uF) should have good high frequency performance including low ESR and low ESL. Panasonic HFQ or FC capacitors are ideal for the bulk capacitor. Zobel Capacitor. Zobel resistor, which in conjunction with CZ, terminates the output filter at high frequencies. The combination of RZ and CZ minimizes peaking of the output filter under both no load conditions or with real world loads, including loudspeakers which usually exhibit a rising impedance with frequency. Schottky diodes that minimize undershoots of the outputs with respect to power ground during switching transitions. For maximum effectiveness, these diodes must be located close to the output pins and returned to their respective PGND. Please see Application/Test Circuit for ground return pin. Schottky diodes that minimize overshoots of the outputs with respect to VDD during switching transitions (required for applications where VDD >13.5V). For maximum effectiveness, these diodes must be located close to the output pins and returned to their respective VDD pins. Please see Application/Test Circuit for VDD return pin. Output inductor, which in conjunction with CO, demodulates (filters) the switching waveform into an audio signal. Forms a second order filter with a cutoff frequency of f C = 1 ( 2 L O C O ) and a quality factor of
Q = RLCO LOCO
CS CSW
CZ RZ
DO
DH
LO
.
CO CDO
Output capacitor. Differential Output Capacitor.
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Typical Performance
100 90 80 70 60 50 40 30 20 10 0 0
Efficiency versus Output Power
RL=8 RL=4
Channel Separation versus Frequency
-40 -50 -60
VDD=14.2V Av=12V/V Fin=1kHz VDD=14.2V Av=12V/V BW=22-22kHz RL=4 Pout=1W/ch
Efficiency (%)
dBr
-70 -80 -90 20
5
10 15 20 Output Power per Channel (W)
25
50
100
200
500 Hz
1k
2k
5k
10k 20k
THD+N versus Frequency
1 0.5 0.2 0.1 0.05 % 0.02 0.01 0.005 0.002 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
VDD=14.2V Av=12V/V BW=22-22kHz Pout=1W/ch
Frequency Response
+1 +0 dBr
RL=4 RL=8
-1 -2 -3 10
VDD=14.2V Av=12V/V BW=22-22kHz RL=4 Pout=1W/ch
20
50
100
200
500 Hz
1k
2k
5k
10k 20k
Intermodulated Distortion
+0 -20 -40 dBr -60 -80 -100 -120 100 200 500 1k 2k Hz 5k 10k 30k
19k/20kHz (1:1) VDD=14.2V Av=12V/V BW=22-80kHz RL=4 0dBr=2Vrms
26 24 22 20 18 16 14 12 10
Output Power versus Supply Voltage
Av=12V/V BW=22-22kHz RL=4
10% THD+N
Output Power (W)
1.0% THD+N
0.1% THD+N
12.00 12.25 12.50 12.75 13.00 13.25 13.50 13.75 14.00 14.25 14.50
Supply Voltage (V)
Noise Floor
-80 -85 -90 -95 dBV -100 -105 -110 -115 -120 100 200 500 1k Hz 2k 5k 10k 20k
VDD=14.2V Av=12V/V BW=22-22kHz RL=4
16 15 14 13 12 11 10 9 8 7 6
Output Power versus Supply Voltage
Av=12V/V BW=22-22kHz RL=8
10% THD+N
Output Power (W)
1.0% THD+N
0.1% THD+N
12.00 12.25 12.50 12.75 13.00 13.25 13.50 13.75 14.00 14.25 14.50
Supply Voltage (V)
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Application Information
Circuit Board Layout
The TA2021B is a power amplifier which operates at relatively high switching frequencies. The outputs of the amplifier switch between VDD and PGND at frequencies as high as 1MHz while driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Because the TA2021B drives the inductive LC output filters and speaker load, the amplifier outputs can be pulled above VDD and below PGND by the stored energy in the output inductance. To avoid subjecting the TA2021B to potentially damaging voltage stress, it is critical to have a good printed circuit board layout to minimize parasitic effects caused by excessive trace inductance/capacitance. It is recommended that Tripath's layout and application circuit be used as closely as possible for all applications and only be deviated from after careful analysis of the effects of any changes.
Output Stage layout Considerations and Component Selection Criteria
Proper PCB layout and component selection is a major step in designing a reliable TA2021B power amplifier. The supply pins require proper decoupling with correctly chosen components to achieve optimal reliability. The output pins need proper protection to keep the outputs from going below ground and above VDD.
The above layout shows component placement and routing for channel 1 (the same design criteria applies to channel 2). This shows that C3, a 0.1uF surface mount 0805 capacitor, should be the first component placed and must decouple VDD1 (pins 29 and 30) directly to PGND1 (pin35). C2, a low ESR, electrolytic capacitor, should also decouple VDD1 directly to PGND1. Both C2 and C3 may decouple VDD1 to a ground plane, but it is critical that the return path to the PGND1 pin of the TA2021B, whether it is a ground plane or a trace, be a short and direct low impedance path. Effectively decoupling VDD will shunt any power supply trace length inductance. The diodes and inductors shown are for channel 1's outputs. D1, D3, and L2 connect to the OUTP1 pin and D2, D4, and L3 connect to the OUTM1 pin of the TA2021B. Each output must have Schottky or Ultra Fast Recovery diodes placed near the TA2021B, preferably immediately
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after the decoupling capacitors and use short returns to PGND1. These low side diodes, D1 and D2, will prevent the outputs from going below ground. To be optimally effective they must have a short and direct return path to its proper ground pin (PGND1) of the TA2021B. This can be achieved with a ground plane or a trace. Additionally, each channel must use Schottky or Ultra Fast Recovery diodes with short returns to VDD if the supply voltage exceeds 13.5V. These high side diodes, D3 and D4, will prevent the outputs from going above VDD. To be optimally effective they must have a short and direct return path to its proper VDD pin (VDD1) of the TA2021B. This can be achieved with a ground plane or a trace. The output inductors, L2 and L3, should be placed close to the TA2021B without compromising the locations of the closely placed supply decoupling capacitors and output diodes. The purpose of placing the output inductors close to the TA2021B output pins is to reduce the trace length of the switching outputs. This will aid in reducing radiated emissions. Please see the External Component Description section on page 6 for more details on the abovementioned components. The Application/ Test Circuit refers to the low side diodes as DO, The high side diodes as DH, and both supply decoupling capacitors as CSW.
TA2021B Amplifier Gain
The gain of the TA2021B is set by the ratio of two external resistors, RI and RF, and is given by the following formula:
VO R = - 12 F VI RI
where VI is the input signal level and VO is the differential output signal level across the speaker. Please note that OUTP1 and OUTP2 are 180 out of phase with their corresponding input signals. 20 watts of RMS output power results from an 8.944 Vrms signal across a four-ohm speaker load. If RF = RI, then 20 Watts will be achieved with 0.745 Vrms of input signal.
8.944 VRMS = (R L PO ) = ( 4 20 W )
Protection Circuits
The TA2021B is guarded against over-temperature and over-current conditions. When the device goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH state indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRISTATED, and will float to 1/2 of VDD.
Over-temperature Protection
An over-temperature fault occurs if the junction temperature of the part exceeds approximately 155C. The thermal hysteresis of the part is approximately 45C, therefore the fault will automatically clear when the junction temperature drops below 110C.
Over-current Protection
An over-current fault occurs if more than approximately 7 amps of current flows from any of the amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the speaker is shorted to ground. An over-current fault sets an internal latch that can only be cleared if the MUTE pin is toggled or if the part is powered down. Alternately, if the MUTE pin is
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connected to the FAULT pin, the HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset the fault condition.
Overload (Output Active Low)
The OVERLOADB pin is a 5V logic active-low output. When low, it indicates that the level of the input signal has overloaded the amplifier resulting in increased distortion at the output. The OVERLOADB signal can be used to control a distortion indicator light or LED through a simple buffer circuit.
Sleep Pin (Input Active High)
The SLEEP pin is a 5V logic input that, when pulled high (>3.5V), puts the part into a low quiescent current mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the pin to be pulled up through a large valued resistor (1M recommended, 100K minimum) to VDD. To disable SLEEP mode, the sleep pin should be grounded.
Fault Pin (Output Active High)
The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over current at any output, and junction temperature greater than approximately 155C. The FAULT output is capable of directly driving an LED through a series 2K resistor. If the FAULT pin is connected directly to the MUTE input an automatic reset will occur in the event of an overcurrent condition.
Performance Measurements of the TA2021B
The TA2021B operates by generating a high frequency switching signal based on the audio input. This signal is sent through an external low-pass filter that recovers an amplified version of the audio input. The frequency of the switching pattern is spread spectrum in nature and typically varies between 100kHz and 1MHz (which is well above the 20Hz - 20kHz audio band). The pattern itself does not alter or distort the audio input signal, but it does introduce some inaudible components. The measurements of certain performance parameters, particularly noise related specifications such as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible noise components introduced by the TA2021B amplifier switching pattern will degrade the measurement. One feature of the TA2021B is that it does not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements. Though using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when they are made with wide-bandwidth measuring equipment), these same filters degrade frequency response. The TA2021B Evaluation Board uses the Application/Test Circuit of this data sheet, which has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument.
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Package Information
36-pin PSOP Package
32 1
E2 2 PLACES
36
Package Dimensions for SLUG-UP
1
18
3.10 REF
E3
E2 2 PLACES
36
19
D1
TOP VIEW
E1
E
BOTTOM VIEW
D
3.35 REF
SEE DETAIL "A"
e
b
SIDE VIEW
Dimension b c D D1 E E1 E2 E3 e L1 L 0.8 M in. 0.22 0.23 15.8 9.4 13.9 10.9 2.9 5.8 Nom. ----15.9 --14.2 11.0 ----0.65 BSC. 0.35 BSC. --1.1 M ax. 0.38
END VIEW
0.2 REF
16 9.8 14.5 11.1 3.2 6.2
GAUGE PLANE
0.32
L1
0.20 +/- 0.10
3.15 +/- 0.15
L
1.60 REF
Note: All dimensions are in millimeters.
DETAIL "A"
11
4 +/- 4
c
E1
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E
Tri path Technol og y, I nc. - Techni cal I nformati on
Preliminary Information
This is a product in development. Tripath Technology, Inc. reserves the right to make any changes without further notice to improve reliability, function and design. Tripath and Digital Power Processing are trademarks of Tripath Technology. Other trademarks referenced in this document are owned by their respective companies. Tripath Technology, Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application of use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. TRIPATH'S PRODUCT ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHONOLOGY, INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury of the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Contact Information
TRIPATH TECHNOLOGY, INC 2560 Orchard Parkway, San Jose, CA 95131 408.750.3000 - P 408.750.3001 - F For more Sales Information, please visit us @ www.tripath.com/cont_s.htm For more Technical Information, please visit us @ www.tripath.com/data.htm
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